Semiconductor calibration structures, semiconductor calibration wafers, calibration methods of calibrating semiconductor wafer coating systems, semiconductor processing methods of ascertaining layer alignment during processing and calibration methods of calibrating multiple semiconductor wafer coating systems

ABSTRACT

Semiconductor wafer coating system calibration structures and methods are described. In one embodiment, a calibration structure includes a perimetral edge bounding a calibration body. A calibration edge is spaced from the perimetral edge and is positioned over the calibration body. Together, the edges define a distance therebetween which is configured to calibrate a wafer coating system. In a preferred embodiment, the edges define respective termination distances configured to calibrate multiple different wafer coating systems. In another embodiment, a calibration pattern is formed over a semiconductor wafer. A layer of material is formed over the calibration pattern by a coating system, and selected portions thereof removed by the system. The positions of unremoved portions of the layer of material are inspected relative to the calibration pattern to ascertain whether the coating system removed the selected portions within desired tolerances. If not, the coating system is calibrated to within desired tolerances.

TECHNICAL FIELD

[0001] The present invention relates to semiconductor calibration structures, semiconductor calibration wafers, calibration methods of calibrating semiconductor wafer coating systems, semiconductor processing methods of ascertaining layer alignment during processing, and calibration methods of calibrating multiple semiconductor wafer coating systems.

BACKGROUND OF THE INVENTION

[0002] During conventional applications of masking layers or photoresist layer coatings to semiconductor wafers, so-called coating systems are typically used. Such systems can include a flat, circular, disk-shaped, rotatable vacuum chuck having a diameter slightly less than that of a semiconductor wafer. The vacuum chuck can be used to hold and rotate a semiconductor wafer during application of the masking layer or photoresist. The vacuum chuck is typically oriented such that a semiconductor wafer placed thereon resides in a level horizontal plane. In operation, the bottom or inactive surface of a semiconductor wafer is placed on the vacuum chuck. The vacuum chuck applies a suction or negative pressure to the bottom surface of the semiconductor wafer to hold the semiconductor wafer thereon.

[0003] Typically, a desired amount of liquid photoresist is applied to the top, upwardly-facing surface of the semiconductor wafer, while the semiconductor wafer is being rotated on the vacuum chuck. Thus, as the semiconductor wafer is rotated, the photoresist material spreads radially outward from the center of the semiconductor wafer and toward the edge of the semiconductor wafer such that the entire top or active surface of the wafer is coated with a layer of photoresist. Excess photoresist material can be sloughed off the wafer during the rotation process. Excess amounts of photoresist, can, however, accumulate and form a mound or bead of photoresist on the outer edge of the semiconductor wafer. In order to eliminate the “edge bead” of photoresist, a coating system known as an edge bead removal unit can be employed.

[0004] Two types of edge bead removal units are well known in the art, chemical and optical. Chemical edge bead removal units include a nozzle which dispenses a solvent referred to as edge bead removal fluid, onto the photoresist at the edge of the semiconductor wafer. The solvent dissolves or develops away the photoresist and allows for easy removal of the photoresist from the edge of the semiconductor wafer. In an optical edge bead removal unit, the photoresist at or near the edge of the semiconductor wafer is exposed to light. During subsequent development processes, the exposed photoresist is removed. Photoresist which remains on the semiconductor wafer forms a mask for subsequent processing operations.

[0005] A problem which has arisen in prior processes involves in advertently removing too much photoresist from the edge of semiconductor wafers thereby exposing substrate layers to undesirable etching operations. Another problem which has arisen in the context of the use of multiple coating systems, as is typical, is the inability to precisely control the amount of material removed as between these multiple coating systems.

[0006] Typically, several different edge bead removal units are utilized during fabrication of integrated circuit devices on semiconductor wafers. The use of different edge bead removal units commonly results in a random or haphazard stacking of substrate layers at or near the edge of the semiconductor wafer. The randomly or haphazardly stacked substrate layers can lift and detrimentally redeposit onto the semiconductor wafer. The redeposited substrate material can contaminate the semiconductor wafer and cause defects in the integrated circuit devices formed on the wafer. Additionally, random or haphazardly stacked layers at the edge of the semiconductor wafer often leave certain substrate layers detrimentally exposed to the ambient.

[0007] Furthermore, random or haphazard stacking of the substrate layers can also result in having a substrate layer inadvertently placed into contact with an underlying substrate layer to which the overlying layer will not stick. In such an instance, the overlying layer will tend to peel from the underlying layer and detrimentally redeposit onto the semiconductor wafer. For example, a metal layer placed directly on top of a polysilicon layer will often peel from the polysilicon layer, thereby contaminating the semiconductor wafer and causing defects in the integrated circuitry devices formed thereon. Methods of forming uniformly-stacked layers for reducing such edge-related defects are described in commonly-assigned U.S. Pat. No. 5,618,380, the disclosure of which is incorporated by reference herein.

[0008] This invention arose out of concerns associated with providing methods and structures for calibrating semiconductor processing equipment, and in particular, wafer coating systems.

SUMMARY OF THE INVENTION

[0009] Semiconductor wafer coating system calibration structures and methods are described. In one embodiment, a calibration structure includes a perimetral edge bounding a calibration body. A calibration edge is spaced from the perimetral edge and is positioned over the calibration body. Together, the edges define a distance therebetween which is configured to calibrate a wafer coating system. In a preferred embodiment, the edges define respective termination distances configured to calibrate multiple different wafer coating systems. In another embodiment, a calibration pattern is formed over a semiconductor wafer. A layer of material is formed over the calibration pattern by a coating system, and selected portions thereof removed by the system. The positions of unremoved portions of the layer of material are inspected relative to the calibration pattern to ascertain whether the coating system removed the selected portions within desired tolerances. If not, the coating system is calibrated to within desired tolerances.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Preferred embodiments of the invention are described below with reference to the following accompanying drawings.

[0011]FIG. 1 is a top plan view of a calibration structure in accordance with one embodiment of the invention.

[0012]FIG. 2 is a top plan view of a calibration structure in accordance with another, more preferred embodiment of the present invention.

[0013]FIG. 3 is a view of the FIG. 2 calibration structure at a processing step which is different from that which is shown in FIG. 2.

[0014]FIG. 4 is a view of the FIG. 3 calibration structure at a processing step which is different from that which is shown in FIG. 3.

[0015]FIG. 5 is a view which is taken along line 5-5 in FIG. 4.

[0016]FIG. 6 is a view which is taken along line 6-6 in FIG. 4.

[0017]FIG. 7 is an enlarged plan view of a portion of the FIG. 6 calibration structure, as it might appear during calibration.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] During the fabrication of integrated circuit devices, numerous substrate layers are deposited over the entire surface of the semiconductor wafer. Commonly, a layer of photoresist material is then applied and spun over the entire surface of each substrate layer. Portions of the photoresist layer are removed from the substrate layer using various processes. The remaining photoresist forms a mask which protects the underlying substrate layer from subsequent processes such as, for example, etching. Edge bead removal processes and systems determine how close to the edge of the semiconductor wafer an underlying substrate layer remains after an etching process. For example, if the edge bead removal process extends inward 3 mm from the edge of the semiconductor wafer, that portion of the underlying substrate layer residing 3 mm from the edge of semiconductor wafer will no longer have photoresist thereon. During subsequent etching processes, the uncovered portion of the underlying substrate layer is removed. Therefore, the remaining underlying substrate layer extends to within 3 mm of the edge of the semiconductor wafer.

[0019] Referring to FIG. 1, a calibration structure is shown generally at 10 and is configured for use with one, and preferably multiple different semiconductor coating systems. As used in this document, the term “coating system” will be understood to refer to a system which both applies and selectively removes a layer of material such as photoresist. Such system can comprise an integral unit, or separate units arranged to function as described above and below. In a preferred embodiment, such systems comprise edge bead removal units, such as chemical edge bead removal units and optical edge bead removal units. The calibration structure(s) described below facilitate calibration of one or more systems, and standardization of multiple different processing units to a predetermined removal standard.

[0020] Calibration structure 10 includes a perimetral or outer edge 12 which bounds a calibration body 14, and that has a shape which defines the periphery of the calibration body. In the illustrated and preferred embodiment, calibration structure 10 comprises a semiconductor wafer such as a silicon wafer.

[0021] A calibration pattern 16 is provided on or over wafer 10. The calibration pattern defines one or more points of reference from which alignment of overlying layers can be judged. In turn, this enables one to ascertain whether an overlying layer is aligned within desired tolerances relative to the calibration pattern. In one preferred embodiment, calibration pattern 16 is provided by forming a layer of material such as oxide, nitride, or the like, over the wafer, and patterning and etching the layer to define the calibration pattern. Preferably, the material comprising the calibration pattern is selected so that the calibration structure can be used over and over again in the context of multiple coating systems. The definition of the calibration pattern preferably forms one or more calibration lines or edges 18 which are spaced inwardly from perimetral edge 12 and positioned over calibration body 14. The preferred calibration edge(s), together with perimetral edge 12 define a distance d_(n), therebetween which is configured to calibrate a wafer coating system as will become apparent below. The calibration pattern set forth in FIG. 1 is but one example of a calibration pattern which can be implemented in accordance with the invention, and is intended to be non-limiting.

[0022] In the illustrated example, calibration edges 18 define, relative to perimetral edge 12, a plurality of spaced, different selected distances. For example, a plurality of distances d₁-d₅ are shown. These distances can represent one or more standards or design tolerances relative to which overlying layers are desired to be formed. The calibration structure can be utilized over and over, in connection with different coating systems to provide an effective standard which is useful for calibrating such systems. The illustrated calibration pattern 16 has a calibration edge 18 (the rightmost calibration edge 18) which has a generally stepped appearance when viewed from over the calibration body. The illustrated calibration pattern also includes a plurality of space-apart, non-contiguous edges 18 (the leftmost calibration edges) which define separate, but related pattern portions. In the illustrated example, distances d₁-d₅ are so-called “termination distances”. A termination distance is simply defined as the distance between the edge of a substrate layer from an edge, e.g. perimetral edge 12, of a wafer.

[0023] Calibration pattern 16 can be considered as including a plurality of calibration edges 18 which, in this example, generally follow the shape of perimetral edge 12. Individual joinder edges 20 are provided and are joined with and extend between differently-spaced calibration edges. The joinder edges extend generally away from perimetral edge 12. In this example, the calibration pattern is distributed about less than an entirety of a wafer portion proximate the periphery. The calibration pattern can, however, be distributed about an entirety of the wafer's periphery, as will become apparent below.

[0024] Referring to FIG. 2, another, more preferred embodiment is set forth generally at 10 a. Like numerals from the above-described embodiment are utilized where appropriate, with differences being indicated with the suffix “a”.

[0025] A different calibration pattern 16 a is provided, and is one in which first and second respective calibration edges 18 a, 18 b define, in part, a generally contiguous calibration pattern which is distributed about an entirety of the wafer's periphery. Edges 18 a, 18 b are disposed in an alternating fashion proximate perimetral edge 12. First and second edges 18 a, 18 b generally follow at least a portion of outer edge 12 and are connected by individual joinder edges 20 a. First and second edges 18 a, 18 b are spaced inwardly of outer edge 12 different respective distances. In the illustrated example, the different respective distances define a specification which includes an allowed variance. For example, distance d_(1a) is approximately 2.3 mm from outer edge 12, while distance d_(2a) is approximately 2.7 mm from outer edge 12. In this example, the specification for a termination distance is 2.5 mm, plus or minus 0.2 mm. Of course, other distances can be used depending on the desired specification; and, more than two termination distances can be defined about the periphery of the wafer.

[0026] In another aspect, the material comprising calibration patterns 16, 16 a (FIGS. 1 and 2) can be selected to provide a visually-or optically-discernable color-contrasting relationship with an underlying layer or the wafer. Such can facilitate visual or other inspection of the wafer as will become apparent below. Accordingly, the calibration pattern can comprise a first color and the wafer, or underlying layer, can comprise a second color intermediate first and second edges 18 a, 18 b and perimetral edge 12, with the second color being different.

[0027] In use, the present invention provides a standard by which one, and preferably more, semiconductor wafer coating systems can be calibrated. This greatly facilitates processing of semiconductor wafers which, in the past and in the context of edge bead removal units, have typically required measurement of termination distances with the use of manual calibers. Such can, to say the least, consume valuable processing time and slow throughput of the wafers.

[0028] FIGS. 3-7 illustrate certain methodical aspects of the present invention in the context of the provided FIG. 2 calibration structure.

[0029] Referring to FIG. 3, calibration structure 10 a is typically placed in a first coating system through which a first or different material layer 22 is formed over calibration pattern 16 a. An exemplary material for layer 22 comprises a masking material such as photoresist.

[0030] Referring to FIG. 4, selected portions of layer 22 are removed sufficient to define a material edge 24, set off for clarity purposes with a dashed line. Where layer 22 comprises photoresist, the removal of the selected portions can comprise exposing the photoresist to selected light, and developing the layer sufficiently to remove selected portions thereof as by an optical edge bead removal process. Such removal or developing can also comprise utilizing a chemical edge bead removal process. Other methods can, of course, be used. Such provides a first patterned masking layer over calibration pattern 16 a.

[0031] Referring to FIGS. 5-7, after removal of the selected portions of layer 22, the position of the patterned masking layer is inspected relative to calibration pattern 16 a, to ascertain whether the coating system utilized to deposit and remove layer 22, did so in a manner which is consistent with, or within desired tolerances. If the selected portions were not removed within the desired tolerances, the coating system can be used to deposit another layer such as layer 22, and again tested to ascertain tolerance conformity. Such can typically involve removing the previously-formed layer 22 entirely from over wafer body 14, reapplying the layer, removing the selected portions after calibration of the coating system, and inspecting the results. The inspection of the unremoved portions of layer 22 can be conducted relative to one or more of the distances defined by first and second edges 18 a, 18 b.

[0032] In a preferred embodiment, inspection of layer 22 comprises determining whether material edge 24 is disposed in a desired position relative to first and second edges 18 a, 18 b. In a most preferred embodiment, inspection comprises ascertaining whether material edge 24 is disposed intermediate or between first and second edges 18 a, 18 b when viewed from over the wafer. Such a range is shown in FIG. 5 and 6 by arrow R. FIG. 7 shows a desired alignment where material edge 24 can be seen to be disposed between or intermediate edges 18 a, 18 b. If material edge 24 falls outside of edge 18 a or inside of edge 18 b, one can ascertain that layer 22 was patterned outside of desired tolerances and hence the coating system is in need of calibration.

[0033] After calibration of a first coating system is either confirmed, or adjusted and reconfirmed, patterned masking layer 22 can be removed from over wafer body 14. Subsequently, a second and different coating system can be used, and a second patterned masking layer can be formed over calibration pattern 16 a substantially as described above with respect to the first patterned masking layer. Subsequently, the position of the second patterned masking layer can be inspected relative to calibration pattern 16 a to ascertain whether the coating system performed within desired tolerances. If not, the coating system can be calibrated to within desired tolerances. In this way, it will be appreciated, multiple different semiconductor wafer coating systems can be calibrated to a common standard. Such systems can include, without limitation, edge bead removal units such as chemical and optical edge bead removal units.

[0034] Calibration structure or wafer 10 provides a standardized structure which can be used over and over, quickly and conveniently between different and unrelated systems. Such greatly facilitates processing of semiconductor wafers which, many times, occurs in an assembly line fashion. Eliminating the need to manually measure, with calibers or other means, the alignment of applied masking layers provides time saving measures which greatly speeds up processing of wafers and increases throughput.

[0035] In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents. 

1. A semiconductor wafer coating system calibration structure comprising: a perimetral edge bounding a calibration body; and a calibration edge spaced from said perimetral edge and positioned over said calibration body, said edges defining a distance therebetween configured to calibrate a wafer coating system.
 2. The calibration structure of claim 1, wherein said calibration edge defines, together with said perimetral edge, a plurality of different distances configured to calibrate said wafer coating system.
 3. The calibration structure of claim 2, wherein said calibration edge has a generally stepped appearance when viewed from over the calibration body.
 4. The calibration structure of claim 1, wherein said calibration edge comprises a plurality of spaced-apart, non-contiguous edges.
 5. The calibration structure of claim 4, wherein said spaced-apart, non-contiguous edges define, together with said perimetral edge, a plurality of different distances configured to calibrate said coating system.
 6. The calibration structure of claim 1, wherein said coating system comprises an edge bead removal unit.
 7. The calibration structure of claim 6, wherein said edge bead removal unit comprises a chemical edge bead removal unit.
 8. The calibration structure of claim 6, wherein said edge bead removal unit comprises an optical edge bead removal unit.
 9. The calibration structure of claim 1, wherein said distance is configured to calibrate multiple different coating systems.
 10. The calibration structure of claim 9, wherein said multiple different coating systems comprise edge bead removal units.
 11. A semiconductor wafer coating system calibration wafer comprising: a perimetral edge bounding a wafer body; and a layer of material disposed over the wafer body and having a calibration edge spaced inwardly of the said perimetral edge, said edges defining termination distances therebetween configured to calibrate multiple different wafer coating systems.
 12. The calibration wafer of claim 11, wherein said multiple different wafer coating systems comprise edge bead removal units.
 13. The calibration wafer of claim 12, wherein one of said edge bead removal units comprises a chemical edge bead removal unit.
 14. The calibration wafer of claim 12, wherein said one of said edge bead removal units comprises an optical edge bead removal unit.
 15. The calibration wafer of claim 11, wherein said calibration edge defines, together with said perimetral edge, a plurality of different distances configured to calibrate said multiple different wafer coating systems.
 16. The calibration wafer of claim 15, wherein said calibration edge has a generally stepped appearance when viewed from over the wafer.
 17. The calibration wafer of claim 15, wherein said calibration edge defines, in part, a generally contiguous calibration pattern.
 18. The calibration wafer of claim 15, wherein said calibration edge comprises a plurality of spaced-apart, non-contiguous edges.
 19. A semiconductor wafer coating system calibration wafer comprising: a perimetral edge bounding a wafer body; and a layer of material disposed over the wafer body and having a calibration edge spaced inwardly of the said perimetral edge, said edges defining a plurality of different termination distances therebetween configured to calibrate an edge bead removal unit.
 20. The calibration wafer of claim 19, wherein said calibration edge is contiguous.
 21. The calibration wafer of claim 19, wherein said calibration edge generally follows the shape of the perimetral edge.
 22. The calibration wafer of claim 19, wherein said calibration edge comprises a plurality of spaced-apart, non-contiguous edges.
 23. A calibration wafer for calibrating a plurality of wafer coating systems comprising: a wafer having an outer edge having a shape which defines the wafer's periphery; a calibration pattern distributed about a portion of said wafer proximate said periphery, said calibration pattern having first and second edges which generally follow at least a portion of said outer edge shape, and one joinder edge joined with one of the first and second edges and extending generally away from the outer edge.
 24. The calibration wafer of claim 23, wherein said calibration pattern comprises a first color, and said wafer comprises a second color intermediate said first and second edges and said wafer's outer edge, said first and second colors being different.
 25. The calibration wafer of claim 23, wherein said first and second edges are spaced inwardly of said wafer's outer edge different respective distances.
 26. The calibration wafer of claim 23, wherein said calibration pattern comprises a plurality of first and second edges, and a plurality of joinder edges joined with individual first and second edges.
 27. The calibration wafer of claim 26, wherein said plurality of first and second edges are spaced inwardly of said wafer's outer edge different respective distances.
 28. The calibration wafer of claim 27, wherein said plurality of first and second edges are disposed in an alternating fashion.
 29. The calibration wafer of claim 27, wherein said calibration pattern comprises a first color, and said wafer comprises a second color intermediate said plurality of said first and second edges and said wafer's outer edge, said first and second colors being different.
 30. A calibration method of calibrating a semiconductor wafer coating system comprising: providing a semiconductor wafer having a calibration pattern; using a coating system, forming a layer of material over the calibration pattern and removing selected portions of the layer of material; and inspecting the position of unremoved portions of the layer of material relative to the calibration pattern to ascertain whether said coating system removed said selected portions within desired tolerances, and if not, calibrating said coating system.
 31. The calibration method of claim 30, wherein said wafer has an outer edge having a shape which defines the wafer's periphery, and: the calibration pattern comprises first and second calibration edges which generally follow at least a portion of said outer edge shape, said removing of said selected portions of said layer of material defines a material edge, and said inspecting comprises determining whether said material edge is disposed in a desired position relative to said first and second edges.
 32. The calibration method of claim 31, wherein said first and second calibration edges are disposed at different respective distances relative to said wafer's outer edge.
 33. The calibration method of claim 32, wherein said inspecting comprises ascertaining whether said material edge is disposed intermediate said first and second edges when viewed from over the wafer.
 34. The calibration method of claim 31, wherein: said first and second calibration edges comprise a plurality of first and second calibration edges at different respective distances relative to said wafer's outer edge, said edges being disposed in an alternating fashion about the wafer's periphery; and said inspecting comprises ascertaining whether said material edge is disposed intermediate the first and second edges when viewed from over the wafer.
 35. A semiconductor processing method of ascertaining layer alignment during processing comprising: forming a layer of material over a calibration substrate, said calibration substrate having a perimetral edge bounding an interior calibration body; patterning and etching said layer of material to define a plurality of calibration edges positioned over said calibration body and spaced different selected distances from said perimetral edge, said distances being configured to calibrate a semiconductor wafer coating system; using a semiconductor wafer coating system, forming a different layer of material over the calibration substrate and removing said different layer sufficient to remove selected portions of the different layer from over the substrate; and inspecting the position of unremoved portions of the different layer of material relative to one of the selected distances to ascertain whether said coating system removed said selected portions within desired tolerances.
 36. The calibration method of claim 35, wherein said removing of said different layer of material defines a material edge, and said inspecting comprises ascertaining whether said material edge is disposed between two of said calibration edges when viewed from over said substrate.
 37. The calibration method of claim 35, wherein said calibration substrate's perimetral edge has a shape which defines the substrate's periphery, and: said patterning and etching comprises forming said calibration edges to generally follow at least a portion of said perimetral edge shape, said removing of said different layer of material defines a material edge, and said inspecting comprises ascertaining whether said material edge is disposed in a desired position relative to said calibration edges when viewed from over said substrate.
 38. The calibration method of claim 37, wherein said inspecting comprises ascertaining whether said material edge is disposed intermediate said first and second edges when viewed from over said substrate.
 39. The calibration method of claim 37, wherein the etching of said layer of material to define said plurality of calibration edges comprising forming said edges to alternate thereby defining different first and second distances relative to said perimetral edge.
 40. A calibration method of calibrating multiple semiconductor wafer coating systems comprising: forming a calibration pattern over a semiconductor wafer; using a first wafer coating system, forming a first patterned masking layer over the calibration pattern; inspecting the position of the first patterned masking layer relative to the calibration pattern to ascertain whether said first coating system formed said first patterned masking layer over the calibration pattern within desired tolerances, and if not, calibrating said first coating system; removing the first patterned masking layer; using a second wafer coating system, forming a second patterned masking layer over the calibration pattern; and inspecting the position of the second patterned masking layer relative to the calibration pattern to ascertain whether said second coating system formed said second patterned masking layer over the calibration pattern within desired tolerances, and if not, calibrating said second coating system.
 41. The calibration method of claim 40, wherein said semiconductor wafer has an outer edge having a shape which defines the wafer's periphery, and said forming of said calibration pattern comprises forming first and second calibration edges which generally follow at least a portion of the outer edge shape.
 42. The calibration method of claim 41, wherein said first and second calibration edges are spaced inwardly of said outer edge different respective distances.
 43. The calibration method of claim 42, wherein said forming of said first and second patterned masking layers comprises forming respective masking layer edges, and said inspecting steps comprise ascertaining whether said respective masking layer edges are disposed intermediate said first and second calibration edges when viewed from over the substrate. 